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hc05p9agrs/d rev 2.0 68HC05P9A specification (general release) december 18, 1995 csic mcu design group oak hill, texas f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
table of contents section title page general release specification rev. 2.0 iii section 1 general description 1.1 features .......................................................................................................... 1-1 1.2 mask options .................................................................................................. 1-2 1.3 mcu structure ................................................................................................ 1-3 1.4 pin assignments ............................................................................................. 1-4 1.5 signal description ........................................................................................... 1-4 1.5.1 v dd and v ss ............................................................................................... 1-4 1.5.2 irq ............................................................................................................. 1-4 1.5.3 osc1 and osc2 ........................................................................................ 1-5 1.5.4 reset ........................................................................................................ 1-5 1.5.5 tcmp .......................................................................................................... 1-5 1.5.6 pa0 through pa7 ........................................................................................ 1-5 1.5.7 sdo/pb5, sdi/pb6, and sck/pb7 ............................................................ 1-6 1.5.8 pc0 through pc7 ........................................................................................ 1-6 1.5.9 pd5 and tcap/pd7 ................................................................................... 1-6 1.6 input/output programming .............................................................................. 1-6 section 2 memory 2.1 rom ................................................................................................................ 2-3 2.2 rom security feature .................................................................................... 2-3 2.3 ram ................................................................................................................ 2-3 section 3 central processing unit 3.1 accumulator (a) .............................................................................................. 3-1 3.2 index register (x) ........................................................................................... 3-1 3.3 condition code register (ccr) ...................................................................... 3-1 3.3.1 h half carry ........................................................................................... 3-1 3.3.2 i interrupt ................................................................................................ 3-2 3.3.3 n negative ............................................................................................. 3-2 3.3.4 z zero ..................................................................................................... 3-2 3.3.5 c carry/borrow ...................................................................................... 3-2 3.4 stack pointer (sp) ........................................................................................... 3-2 3.5 program counter (pc) .................................................................................... 3-3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification mc68HC05P9A iv rev. 2.0 table of contents section title page section 4 interrupts 4.1 hardware controlled interrupt sequence ........................................................ 4-2 4.2 timer interrupt ................................................................................................. 4-3 4.3 external interrupt ............................................................................................. 4-4 4.4 optional external interrupts (pa0-pa7) ........................................................... 4-6 4.5 software interrupt (swi) ................................................................................. 4-6 section 5 resets 5.1 power-on reset (por) .................................................................................. 5-1 5.2 reset pin ...................................................................................................... 5-1 5.3 computer operating properly (cop) reset .................................................... 5-1 section 6 low power modes 6.1 stop instruction.............................................................................................. 6-1 6.2 stop mode ....................................................................................................... 6-1 6.3 halt mode......................................................................................................... 6-2 6.2 wait instruction............................................................................................... 6-2 section 7 simple serial input/output port 7.1 signal format .................................................................................................. 7-1 7.1.1 serial clock (sck) ...................................................................................... 7-1 7.1.2 serial data out (sdo) ................................................................................ 7-2 7.1.3 serial data in (sdi) ..................................................................................... 7-2 7.2 siop registers ............................................................................................... 7-3 7.2.1 siop control register (scr) ..................................................................... 7-3 7.2.2 siop status register (ssr) ....................................................................... 7-4 7.2.3 siop data register (sdr) ......................................................................... 7-5 section 8 timer 8.1 counter ........................................................................................................... 8-2 8.2 output compare register ............................................................................... 8-3 8.3 input capture register .................................................................................... 8-4 8.4 timer control register (tcr) $12 .................................................................. 8-5 8.5 timer status register (tsr) $13 .................................................................... 8-6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
table of contents section title page general release specification rev. 2.0 v 8.6 timer during wait mode ................................................................................. 8-7 8.7 timer during stop mode ................................................................................. 8-7 section 9 computer operating properly (cop) 9.1 resetting the cop ......................................................................................... 9-1 9.2 cop during wait mode ................................................................................... 9-1 9.3 cop during stop mode .................................................................................. 9-1 section 10 analog-to-digital (a/d) converter 10.1 conversion process ....................................................................................... 10-1 10.2 a/d status and control register (adscr) .................................................... 10-2 10.3 a/d data register (addr)............................................................................. 10-3 10.4 a/d converter during wait mode................................................................... 10-4 10.5 a/d converter during stop or halt mode....................................................... 10-4 section 11 self-check mode section 12 instruction set 12.1 addressing modes ........................................................................................ 12-1 12.1.1 inherent ..................................................................................................... 12-1 12.1.2 immediate ................................................................................................. 12-2 12.1.3 direct ........................................................................................................ 12-2 12.1.4 extended ................................................................................................... 12-2 12.1.5 indexed, no offset .................................................................................... 12-2 12.1.6 indexed, 8-bit offset ................................................................................. 12-2 12.1.7 indexed, 16-bit offset ............................................................................... 12-3 12.1.8 relative ..................................................................................................... 12-3 12.2 instruction types ........................................................................................... 12-4 12.2.1 register/memory instructions ................................................................... 12-4 12.2.3 read-modify-write instructions ................................................................ 12-5 12.2.4 jump/branch instructions ......................................................................... 12-5 12.2.5 bit manipulation instructions ..................................................................... 12-7 12.2.6 control instructions ................................................................................... 12-7 12.3 instruction set summary ............................................................................... 12-8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification mc68HC05P9A vi rev. 2.0 table of contents section title page section 13 electrical specifications 13.1 maximum ratings ......................................................................................... 13-1 13.2 thermal characteristics ................................................................................ 13-1 13.3 dc electrical characteristics ......................................................................... 13-2 13.4 a/d converter characteristics........................................................................ 13-4 13.4 siop timing................................................................................................... 13-5 13.5 control timing................................................................................................ 13-6 section 14 mechanical specifications 14.1 28-pin plastic dual in-line package (case 710-02) ..................................... 14-1 14.2 28-pin small outline integrated circuit package (case 751f-04) ................ 14-2 section 15 ordering information 15.1 mcu ordering forms .................................................................................... 15-1 15.2 application program media ........................................................................... 15-2 15.3 rom program verification ............................................................................ 15-3 15.4 rom verification units (rvus) ..................................................................... 15-3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification rev. 2.0 vii list of figures figure title page 1-1 block diagram ........................................................................................... 1-3 1-2 pin assignments ........................................................................................ 1-4 1-3 port a pullup option .................................................................................. 1-5 1-4 i/o circuitry ................................................................................................ 1-7 2-1 memory map .............................................................................................. 2-1 2-2 i/o registers for the mc68HC05P9A ........................................................ 2-2 4-1 hardware interrupt flowchart .................................................................... 4-3 4-2 irq function block diagram ...................................................................... 4-4 5-1 power-on reset and reset .................................................................... 5-2 6-1 stop/wait flowcharts ............................................................................. 6-3 7-1 siop block diagram .................................................................................. 7-1 7-2 serial i/o port timing ................................................................................ 7-2 7-3 siop control register ............................................................................... 7-3 7-4 siop status register ................................................................................. 7-4 7-5 siop data register ................................................................................... 7-5 8-1 timer block diagram ................................................................................. 8-2 8-2 timer control register ............................................................................... 8-5 8-3 timer status register ................................................................................ 8-6 10-1 a/d status and control register (adscr)............................................... 10-2 10-2 a/d data register (addr) ....................................................................... 10-3 11-1 self-check circuit .................................................................................... 12-2 13-1 siop timing diagram .............................................................................. 13-5 13-2 stop recovery timing ........................................................................... 13-7 13-3 external interrupt timing ......................................................................... 13-7 13-4 power-on reset timing .......................................................................... 13-8 13-5 external reset timing ............................................................................. 13-8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification mc68HC05P9A viii rev. 2.0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
list of tables table title page general release specification rev. 2.0 ix 1-1 i/o pin functions ............................................................................................. 1-7 4-1 vector address for interrupts and reset ......................................................... 4-2 10-1 a/d input selection ........................................................................................ 10-3 11-1 self-check results ........................................................................................ 11-1 12-1 register/memory instructions ....................................................................... 12-4 12-2 read-modify-write instructions ..................................................................... 12-5 12-3 jump and branch instructions ....................................................................... 12-6 12-4 bit manipulation instructions ......................................................................... 12-7 12-5 control instructions ....................................................................................... 12-7 12-6 instruction set summary ............................................................................... 12-8 12-7 opcode map ................................................................................................ 12-14 13-1 dc electrical characteristics (v dd = 5 v) ..................................................... 13-2 13-2 dc electrical characteristics (v dd = 3.3 v) .................................................. 13-3 13-3 a/d converter characeristics......................................................................... 13-4 13-4 siop timing (v dd = 5 v) .............................................................................. 13-5 13-5 siop timing (v dd = 3.3 v) ........................................................................... 13-5 13-6 control timing (v dd = 5 v) ........................................................................... 13-6 13-7 control timing (v dd = 3.3 v) ........................................................................ 13-6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification mc68HC05P9A x rev. 2.0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification general description rev. 2.0 1-1 section 1 general description the mc68HC05P9A is a 28-pin device based on the mc68hc05p9. the memory map includes 2112 bytes of user rom and 128 bytes of ram. the mcu has two 8-bit input/output (i/o) ports, a and c. port b has three i/o pins and port d has two pins, one that is i/o and the other input only. the mc68HC05P9A includes a four-channel 8-bit analog-to-digital (a/d) converter, a simple serial i/o peripheral (siop), and an on-chip mask programmable computer operating properly (cop) watchdog circuit. 1.1 features ? low cost ? hc05 core ? 28-pin package ? on-chip oscillator with rc or crystal/ceramic resonator mask options ? 2112 bytes of user rom including 16 user vector locations ? rom security feature ? 128 bytes of on-chip ram ? 16-bit timer ? 20 bidirectional i/o lines, one input-only line ? mask programmable keyscan (pullups and interrupt) on eight port pins (pa0 through pa7) ? two port pins with high current drive capability (pc0, pc1) ? user mode ? four-channel 8-bit a/d converter ? self-check mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification general description mc68HC05P9A 1-2 rev. 2.0 ? power-saving stop and wait modes ? stop conversion to halt mode (mask option) ? edge-sensitive or edge- and level-sensitive interrupt trigger mask option ? simple serial input/output port ? mask option selectable watchdog timer (cop) 1.2 mask options there are 13 mask options on the mc68HC05P9A: ? clock (rc or crystal) ? irq (edge-sensitive only or edge- and level-sensitive) ? siop (msb or lsb first) ? cop watchdog timer (enable/disable) ? keyscan pullups and interrupts on port a (enable/disable by pin). ? stop instruction (option to convert to halt) all mask options and the user rom are programmed on the 04e layer in fabrication. note negative true signals like reset and irq will be denoted with an overline. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification general description rev. 2.0 1-3 1.3 mcu structure figure 1-1 shows the structure of the mc68HC05P9A. figure 1-1. block diagram internal processor clock port d register data dir register sdo/pb5 sdi/pb6 sck/pb7 accumulator index register condition code register stack pointer program counter high program counter low cpu control alu cpu oscillator and divide by 2 reset irq osc1 osc2 timer system cop system 128 x 8 ram 240 x 8 self- check pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port a i/o lines pc0 pc1 pc2 pc3/an3 pc4/an2 pc5/an1 pc6/an0 pc7/v rh data direction register port c register port c i/o lines pd5 tcmp port d i/o lines tcap/pd7 2112 x 8 user rom data direction register port a register port b reg data dir reg port b i/o lines a/d converter an3 an2 an1 an0 v rh sdo sdi sck serial i/o port (siop) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification general description mc68HC05P9A 1-4 rev. 2.0 1.4 pin assignments the mc68HC05P9A pin assignments are shown in figure 1-2. figure 1-2. pin assignments 1.5 signal description the following paragraphs provide a description of the signals. 1.5.1 v dd and v ss power is supplied to the microcontroller through v dd and v ss . v dd is the power supply and v ss is ground. 1.5.2 irq this pin has a mask option that provides two different choices of interrupt triggering sensitivity. the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. refer to section 3 central processing unit for more detail. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27 28 v dd osc1 osc2 tcap/pd7 tcmp pd5 pc0 pc1 reset irq pa7 pa5 pa4 pa3 pa2 pa1 pa0 pa6 15 16 17 18 19 20 sdo/pb5 sdi/pb6 sck/pb7 v ss 21 22 23 24 25 26 pc2 pc3/an3 pc4/an2 pc5/an1 pc6/an0 pc7/v rh f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification general description rev. 2.0 1-5 1.5.3 osc1 and osc2 these pins provide control input for an on-chip clock oscillator circuit. a crystal, a ceramic resonator, a resistor/capacitor combination, or an external signal connects to these pins and provides a system clock. a mask option selects either a crystal/ceramic resonator or a resistor/capacitor as the frequency determining element. the oscillator frequency is two times the internal bus rate. 1.5.4 reset this active low pin is used to reset the mcu to a known start-up state by pulling reset low. the reset pin contains an internal schmitt trigger as part of its input to improve noise immunity. 1.5.5 tcmp this pin provides an output for the output compare feature of the on-chip timer system. 1.5.6 pa0 through pa7 port a is an 8-bit bidirectional port which does not share any of its pins with other subsystems. the port a data register is at $0000, and the data direction register is at $0004. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. port a has mask option enabled pullup devices and interrupt capability by pin. for a detailed description of i/o programming, refer to 1.6 input/output programming . figure 1-3. port a pullup option pa0 v dd v dd ddr bit normal port from all other port a pins irq schmitt trigger to interrupt logic mask option circuitry f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification general description mc68HC05P9A 1-6 rev. 2.0 1.5.7 sdo/pb5, sdi/pb6, and sck/pb7 port b is a 3-bit bidirectional port. these pins are shared with the siop subsystem. refer to section 7 simple serial input/output port for a detailed description of the siop. the address of the port b data register is $0001 and the data direction register is at address $0005. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. 1.5.8 pc0 through pc2, pc3/an3, pc4/an2, pc5/an1, pc6/an0, pc7/v rh port c, as an 8-bit shared function port, shares ?ve of its pins with the a/d converter. when the a/d converter is not enabled, pc7Cpc0 form an 8-bit general-purpose bidirectional i/o port. the contents of data direction register c (ddrc) determine whether each pin is an input or an output. when the a/d converter is enabled, pc7 becomes v rh , and pc6Cpc3 become an0Can3 (analog inputs 0C3). the values of ch1 and ch0 in the a/d status and control register (adscr) select one of the four pins as the input to the a/d converter. when the a/d converter is enabled a digital read of port c gives a logical zero from the selected analog input pin. a digital read of port cs remaining pins gives their correct digital values. v rh is the positive (high) reference voltage for the a/d converter. v ss is the negative (low) reference voltage. a reset turns off the a/d converter and con?gures port c as a general-purpose i/o port. see section 10 analog-to-digital (a/d) converter . the address of the port c data register is $0002 and the data direction register is at address $0006. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. two of the port c pins, pc0 and pc1, have a higher current drive capability. see section 13 electrical specifications . 1.5.9 pd5 and tcap/pd7 port d is a 2-bit port. pd5 is i/o and tcap/pd7 is input-only shared with the timer input capture. the address of the port d data register is $0003 and the data direction register is at address $0007. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. the tcap/pd7 pin controls the input capture feature for the on-chip programmable timer. this pin can be read at any time even if the tcap function is enabled. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification general description rev. 2.0 1-7 1.6 input/output programming port pins may be programmed as inputs or outputs under software control. the direction of the pins is determined by the state of the corresponding bit in the port data direction register (ddr). each i/o port has an associated ddr. any i/o port pin is con?gured as an output if its corresponding ddr bit is set to a logic one. a pin is con?gured as an input if its corresponding ddr bit is cleared to a logic zero. at power-on or reset, all ddrs are cleared, which con?gures all pins as inputs. the data direction registers are capable of being written to or read by the processor. during the programmed output state, a read of the data register actually reads the value of the output data latch and not the i/o pin. for further information, see table 1-1 and figure 1-4. figure 1-4. i/o circuitry table 1-1. i/o pin functions r/ w ddr i/o pin function 0 0 the i/o pin is in input mode. data is written into the output data latch. 0 1 data is written into the output data latch and output to the i/o pin. 1 0 the state of the i/o pin is read. 1 1 the i/o pin is in an output mode. the output data latch is read. r/ w is an internal signal. data direction register bit latched output data bit i/o pin input reg bit input i/o output internal hc05 connections f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification general description mc68HC05P9A 1-8 rev. 2.0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification memory rev. 2.0 2-1 section 2 memory the mc68HC05P9A has an eight kbyte memory map, consisting of user rom, user ram, self-check rom, and i/o. see figure 2-1 and figure 2-2 . $0000 i/o 32 bytes 0000 $0020 user rom (page zero) 48 bytes 0032 $0050 unused (48 bytes) 0080 $0080 ram 128 bytes 0128 - stack 64 bytes $0100 user rom 2048 bytes 0256 $900 unused 5632 bytes 2304 $1f00 self-check rom 240 bytes 7936 $1fe0 self-check vectors 8160 $1ff0 $1fff user vectors 16 bytes 8176 8191 figure 2-1. memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification memory mc68HC05P9A 2-2 rev. 2.0 address $0000 to $001f data 76543210 $00 port a data $01 port b data 00000 $02 port c data $03 port d data 0 10000 $04 port a ddr $05 port b ddr 11111 $06 port c ddr $07 port d ddr 0 0 00000 $08 unused $09 unused $0a serial ctrl 0 spe 0 mstr 0000 $0b serial stat spf dcol 000000 $0c serial data $0d unused $0e unused $0f unused $10 unused $11 unused $12 timer control icie ocie toie 0 0 0 iedg olvl $13 timer status icf ocf tof 00000 $14 capture high $15 capture low $16 compare high $17 compare low $18 counter high $19 counter low $1a dual tm high $1b dual tm low $1c unused $1d addr $1e adscr ccf adrc adon 0 0 0 ch1 ch0 $1f reserved figure 2-2. i/o registers for the mc68HC05P9A f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification memory rev. 2.0 2-3 2.1 rom the user rom consists of 48 bytes of page zero rom from $0020 to $004f, 2048 bytes of rom from $0100 to $08ff, and 16 bytes of user vectors from $1ff0 to $1fff. the self-check rom and vectors are located from $1f00 to $1fef. 2.2 rom security feature a security feature has been incorporated into the mc68HC05P9A to help prevent external reading of code in the rom. placing unique customer code at rom locations $0028-$002f aids in keeping customer developed software proprietary. 2.3 ram the user ram consists of 128 bytes of a shared stack area. the stack begins at address $00ff. the stack pointer can access 64 bytes of ram in the range $00ff to $00c0. note using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification memory mc68HC05P9A 2-4 rev. 2.0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification central processing unit rev. 2.0 3-1 section 3 central processing unit this section describes the ?ve cpu registers. cpu registers are not part of the memory map. 3.1 accumulator (a) the accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 3.2 index register (x) the index register is an 8-bit register used for the indexed addressing value to create an effective address. the index register also may be used as a temporary storage area. 3.3 condition code register (ccr) the ccr is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the ?fth bit indicates whether interrupts are masked. these bits can be tested individually by a program, and speci?c actions can be taken as a result of their state. each bit is explained in the following paragraphs. 3.3.1 h half carry this bit is set during add and adc operations to indicate that a carry occurred between bits 3 and 4. 70 a 70 x ccr h i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification central processing unit mc68HC05P9A 3-2 rev. 2.0 3.3.2 i interrupt when this bit is set, timer and external interrupts are masked (disabled). if an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the interrupt bit is cleared. 3.3.3 n negative when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. 3.3.4 z zero when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. 3.3.5 c carry/borrow when set, this bit indicates that a carry or borrow out of the arithmetic logical unit (alu) occurred during the last arithmetic operation. this bit is also affected during bit test and branch instructions and during shifts and rotates. 3.4 stack pointer (sp) the stack pointer contains the address of the next free location on the stack. during an mcu reset or the reset stack pointer (rsp) instruction, the stack pointer is set to location $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the seven most signi?cant bits are permanently set to 0000011. these seven bits are appended to the six least signi?cant register bits to produce an address within the range of $00ff to $00c0. subroutines and interrupts may use up to 64 (decimal) locations. if 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. a subroutine call occupies two locations on the stack; an interrupt uses ?ve locations. 12 7 0 0000011 sp f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification central processing unit rev. 2.0 3-3 3.5 program counter (pc) the program counter is a 13-bit register that contains the address of the next byte to be fetched. note the hc05 cpu core is capable of addressing a 64 kbyte memory map. for this implementation, however, the addressing registers are limited to an 8 kbyte memory map. 12 0 pc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification central processing unit mc68HC05P9A 3-4 rev. 2.0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification interrupts rev. 2.0 4-1 section 4 interrupts the mcu can be interrupted four different ways: the two maskable hardware interrupts ( irq and timer), the non-maskable software interrupt instruction (swi), and by the optional external asynchronous interrupt on each port a pin (enabled by pullup mask option). interrupts cause the processor to save register contents on the stack and to set the interrupt mask (i bit) to prevent additional interrupts. the rti instruction causes the register contents to be recovered from the stack and normal processing to resume. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. note the current instruction is the one already fetched and being operated on. when the current instruction is complete, the processor checks all pending hardware interrupts. if interrupts are not masked (ccr i bit clear) and if the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced ?rst. the swi is executed the same as any other instruction, regardless of the i-bit state. table 4-1 lists vector addresses for all interrupts including reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification interrupts mc68HC05P9A 4-2 rev. 2.0 4.1 hardware controlled interrupt sequence the following three functions ( reset, stop, and wait) are not interrupts in the strictest sense. however, they are acted upon in a similar manner. flowcharts for hardware interrupts are shown in figure 4-1, and for stop and wait in figure 6- 1. a discussion is provided below. 1. reset a low input on the reset input pin causes the program to vector to its starting address, which is speci?ed by the contents of memory locations $1ffe and $1fff. the i bit in the condition code register also is set. much of the mcu is con?gured to a known state during this type of reset as described in section 5 resets . 2. stop the stop instruction causes the oscillator to be turned off and the processor to "sleep" until an external interrupt ( irq) or reset occurs.see 6.1.1 stop mode . 3. wait or halt the wait or halt instruction causes all processor clocks to stop, but leaves the timer clock running. this rest state of the processor can be cleared by reset, an external interrupt ( irq), or timer interrupt. these individual interrupts have no special wait vectors. see 6.1.2 halt mode . table 4-1. vector address for interrupts and reset register flag name interrupts cpu interrupt vector address n/a n/a reset reset $1ffe-$1fff n/a n/a software swi $1ffc-$1ffd n/a n/a external interrupt irq $1ffa-$1ffb tsr icf timer input capture timer $1ff8-$1ff9 tsr ocf timer output capture timer $1ff8-$1ff9 tsr tof timer overflow timer $1ff8-$1ff9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification interrupts rev. 2.0 4-3 4.2 timer interrupt three different timer interrupt ?ags cause a timer interrupt when they are set and enabled. the interrupt ?ags are in the timer status register (tsr), and the enable bits are in the timer control register (tcr). any of these interrupts will vector to the same interrupt service routine, located at the address speci?ed by the contents of memory location $1ff8 and $1ff9. from reset external interrupt irq internal interrupt timer i bit set is load pc from: irq: $1ffa-$1ffb timer: $1ff8-$1ff9 set i bit stack pc, x, a, cc clear irq request latch complete interrupt routine and execute rti fetch next instruction execute instruction y y y n n n figure 4-1. hardware interrupt flowchart f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification interrupts mc68HC05P9A 4-4 rev. 2.0 4.3 external interrupt the irq pin drives an asynchronous interrupt to the cpu. an edge detector ?ip- ?op is latched on the falling edge of irq. if either the output from the internal edge detector ?ip-?ops or the level on the irq pin is low, a request is synchronized to the cpu to generate the irq interrupt. if the edge-sensitive only mask 0ption is selected, the output of the internal edge detector ?ip-?op is sampled and the input level on the irq pin is ignored. the interrupt service routine address is speci?ed by the contents of memory locations $1ffa and $1ffb. a block diagram of the irq function is shown in figure 4-2. note the internal interrupt latch is cleared nine ph2 clock cycles after the interrupt is recognized (after location $1ffa is read). therefore, another external interrupt pulse can be latched during the irq service routine. note when the edge- and level-sensitive mask option is selected, the voltage applied to the irq pin must return to the high state before the rti instruction in the interrupt service routine is executed to avoid the processor re-entering the irq service routine. figure 4-2. irq function block diagram irq latch r v dd irq pin mask option (irq level) to irq processing in cpu to bih & bil instruction sensing rst irq vector fetch pa7 ddra7 pa0 ddra0 pa0 irq inhibit (mask option) pa7 irq inhibit (mask option) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification interrupts rev. 2.0 4-5 the irq pin is one source of an irq interrupt and a mask option can also enable the port a pins (pa0 thru pa7) to act as other irq interrupt sources. these sources are all combined into a single oring function to be latched by the irq latch. any enabled irq interrupt source sets the irq latch on the falling edge of the irq pin or a port a pin if port a interrupts have been enabled. if edge-only sensitivity is chosen by a mask option, only the irq latch output can activate a request to the cpu to generate the irq interrupt sequence. this makes the irq interrupt sensitive to the following cases: 1. falling edge on the irq pin with all enabled port a interrupt pins at a high level. 2. falling edge on any enabled port a interrupt pin with all other enabled port a interrupt pins and the irq pin at a high level. if level sensitivity is chosen, the active high state of the irq input can also activate an irq request to the cpu to generate the irq interrupt sequence. this makes the irq interrupt sensitive to the following cases: 1. low level on the irq pin. 2. falling edge on the irq pin with all enabled port a interrupt pins at a high level. 3. low level on any enabled port a interrupt pin. 4. falling edge on any enabled port a interrupt pin with all enabled port a interrupt pins on the irq pin at a high level. this interrupt is serviced by the interrupt service routine located at the address speci?ed by the contents of $1ffa and $1ffb. the irq latch is automatically cleared by entering the interrupt service routine. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification interrupts mc68HC05P9A 4-6 rev. 2.0 4.4 optional external interrupts (pa0-pa7) the irq interrupt can be triggered by the inputs on the pa0 thru pa7 port pins if enabled by individual mask options. with pullup enabled, each port a pin can activate the irq interrupt function and the interrupt operation will be the same as for inputs to the irq pin. once enabled by mask option, each individual port a pin can be disabled as an interrupt source if its corresponding ddr bit is con?gured for output mode. note the bih and bil instructions apply to the output of the logic or function of the enabled pa0 thru pa7 interrupt pins and the irq pin. the bih and bil instructions do not exclusively test the state of the irq pin. note if enabled, the pa0 thru pa7 pins will cause an irq interrupt only if these individual pins are con?gured as inputs. 4.5 software interrupt (swi) the swi is an executable instruction and a non-maskable interrupt. it is executed regardless of the state of the i bit in the ccr. if the i bit is zero (interrupts enabled), swi executes after interrupts which were pending when the swi was fetched but before interrupts generated after the swi was fetched. the interrupt service routine address is speci?ed by the contents of memory locations $1ffc and $1ffd. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification resets rev. 2.0 5-1 section 5 resets the mcu can be reset three ways: by the initial power-on reset function, by an active low input to the reset pin, and by a computer operating properly (cop) watchdog-timer timeout. 5.1 power-on reset (por) an internal reset is generated on power-up to allow the internal clock generator to stabilize. the power-on reset is strictly for power turn-on conditions and should not be used to detect a drop in the power supply voltage. there is a 4064 internal processor clock cycle (t cyc ) oscillator stabilization delay after the oscillator becomes active. if the reset pin is low at the end of this 4064- cycle delay, the mcu will remain in the reset condition until reset goes high. 5.2 reset pin the mcu is reset when a logic zero is applied to the reset input for a period of one and one-half machine cycles (t cyc ). 5.3 computer operating properly (cop) reset the mcu contains a watchdog timer that automatically times out if not reset (cleared) within a speci?c time by a program reset sequence. if the cop watchdog timer is allowed to time-out, an internal reset is generated to reset the mcu. because the internal reset signal is used, the mcu comes out of a cop reset in the same operating mode it was in when the cop time-out was generated. the cop reset function is enabled or disabled by a mask option. refer to section 9 computer operating properly (cop) for more information on the cop. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification resets mc68HC05P9A 5-2 rev. 2.0 osc1 2 reset internal clock 1 internal address bus 1 1ffe 1fff new new new op pch pcl v dd v dd threshold (1-2 v typical) t vddr t oxov 4064 t cyc t cyc t rl internal data bus 1 1ffe 1ffe 1ffe 1ffe new 1fff pch pcl op code code pcl pch notes: 1. internal timing signal and bus information not available externally. 2. osc1 line is not meant to represent frequency. it is only used to represent time. 3. the next rising edge of the internal processor clock following the rising edge of reset initiates the reset sequence. 3 pc pc figure 5-1. power-on reset and reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification low power modes rev. 2.0 6-1 section 6 low power modes the mc68HC05P9A is capable of running in a low-power mode in each of its con?gurations. the wait and stop instructions provide two modes that reduce the power required for the mcu by stopping various internal clocks and/or the on- chip oscillator. the stop and wait instructions are not normally used if the cop watchdog timer is enabled. the stop conversion mask option is used to modify the behavior of the stop instruction from stop mode to halt mode. the ?ow of the stop, halt, and wait modes is shown in figure 6-1. 6.1 stop instruction the stop instruction can result in one of two modes of operation, depending on the stop conversion mask option. if the stop conversion is not chosen, the stop instruction will behave like a normal stop instruction in the mc68hc05 family and place the mcu in the stop mode. if the stop conversion is chosen, the stop instruction will behave like a wait instruction (with the exception of a variable delay at startup) and place the mcu in the halt mode. 6.1.1 stop mode execution of the stop instruction without conversion to halt places the mcu in its lowest power consumption mode. in the stop mode the internal oscillator is turned off, halting all internal processing, including the cop watchdog timer. execution of the stop instruction automatically clears the i bit in the condition code register so that the irq external interrupt is enabled. all other registers and memory remain unaltered. all input/output lines remain unchanged. the mcu can be brought out of the stop mode only by an irq external interrupt or an externally generated reset. when exiting the stop mode, the internal oscillator will resume after a 4064 ph2 clock cycle oscillator stabilization delay. note execution of the stop instruction without conversion to halt (via mask option) will cause the oscillator to stop, and therefore disable the cop watchdog timer. if the cop watchdog timer is used, the stop mode should be changed to the halt mode by selecting the appropriate mask option. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification low power modes mc68HC05P9A 6-2 rev. 2.0 6.1.2 halt mode execution of the stop instruction with the conversion to halt places the mcu in this low-power mode. halt mode consumes the same amount of power as wait mode. (both halt and wait modes consume more power than stop mode.) in halt mode the ph2 clock is halted, suspending all processor and internal bus activity. internal timer clocks remain active, permitting interrupts to be generated from the 16-bit timer or a reset to be generated from the cop watchdog timer. execution of the stop instruction automatically clears the i bit in the condition code register enabling the irq external interrupt. all other registers, memory, and input/output lines remain in their previous states. if the 16-bit timer interrupt is enabled, the processor will exit the halt mode and resume normal operation. the halt mode can also be exited when an irq external interrupt or external reset occurs. when exiting the halt mode, the ph2 clock will resume after a delay of one to 4064 ph2 clock cycles. this varied delay time is the result of the halt mode exit circuitry testing the oscillator stabilization delay timer (a feature of the stop mode), which has been free-running (a feature of the wait mode). note the halt mode is not intended for normal use. this feature is provided to keep the cop watchdog timer active in the event a stop instruction is inadvertently executed. 6.2 wait instruction the wait instruction places the mcu in a low-power mode, which consumes more power than the stop mode. in wait mode, the ph2 clock is halted, suspending all processor and internal bus activity. internal timer clocks remain active, permitting interrupts to be generated from the 16-bit timer and reset to be generated from the cop watchdog timer. execution of the wait instruction automatically clears the i bit in the condition code register enabling the irq external interrupt. all other registers, memory, and input/output lines remain in their previous state. if the 16-bit timer interrupt is enabled, it will cause the processor to exit the wait mode and resume normal operation. the 16-bit timer may be used to generate a periodic exit from the wait mode. the wait mode may also be exited when an irq external interrupt or reset occurs. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification low power modes rev. 2.0 6-3 figure 6-1. stop/wait flowcharts 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine wait stop to halt mask y n external reset? y n irq external interrupt? y n stop external oscillator, stop internal timer clock, reset startup delay restart external oscillator, restart stabilization delay stop internal processor clock, clear i-bit in ccr end of stabilization delay? y n irq external interrupt? y n external oscillator active and internal timer clock active restart internal processor clock stop internal processor clock, clear i-bit in ccr timer internal interrupt? y n external reset? y n stop halt external reset? y n irq external interrupt? y n stop internal processor clock, clear i-bit in ccr external oscillator active and internal timer clock active timer internal interrupt? y n cop internal reset? y n cop internal reset? y n f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification low power modes mc68HC05P9A 6-4 rev. 2.0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification simple serial input/output port rev. 2.0 7-1 section 7 simple serial input/output port this device includes a simple synchronous serial i/o port. the siop is a three wire master/slave system including serial clock (sck), serial data input (sdi), and serial data output (sdo). a mask programmable option determines whether the siop is msb or lsb ?rst. 7.1 signal format the following paragraphs describe the siop signal format. 7.1.1 serial clock (sck) the state of sck between transmissions and prior to enabling the siop must be logic one. the ?rst falling edge of sck signals the beginning of a transmission. at this time, the ?rst bit of received data is accepted at the sdi pin and the ?rst bit of transmitted data is presented at the sdo pin. data is captured at the sdi pin on the rising edge of sck. subsequent falling edges shift the data and accept or present the next bit. the transmission is ended upon the eighth rising edge of sck. the maximum frequency of sck in slave mode is equal to e (bus clock) divided by four. that is, for a 4-mhz oscillator input, e becomes 2 mhz and the maximum sck frequency is 0.5 mhz. there is no minimum sck frequency. figure 7-1. siop block diagram 8-bit shift register d q r c reset sdo sck sdi msb/lsb mask option data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification simple serial input/output port mc68HC05P9A 7-2 rev. 2.0 in master mode, the format is identical except that the sck pin is an output and the shift clock now originates internally. the master mode transmission frequency is ?xed at e/4. 7.1.2 serial data out (sdo) a mask programmable option will be included to allow data to be transmitted in either msb ?rst format or lsb ?rst format. in either case, the state of the sdo pin always will re?ect the value of the ?rst bit received on the previous transmission if there was one. prior to enabling the siop, pb5 can be initialized to determine the beginning state if necessary. while the siop is enabled, pb5 can not be used as a standard output since that pin is coupled to the last stage of the serial shift register. on the ?rst falling edge of sck, the ?rst data bit to be shifted out is presented to the output pin. 7.1.3 serial data in (sdi) the sdi pin becomes an input as soon as the siop is enabled. new data may be presented to the sdi pin on the falling edge of sck. valid data must be present at least 100 ns before the rising edge of the clock and remain valid for 100 ns after the edge. sdo bit 1 bit 2 bit 3 bit 7 sck bit 8 sdi bit 1 bit 2 bit 3 bit 7 bit 8 figure 7-2. serial i/o port timing f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification simple serial input/output port rev. 2.0 7-3 7.2 siop registers the following paragraphs describe the siop registers. 7.2.1 siop control register (scr) this register is located at address $000a and contains two bits. spe serial peripheral enable when set, this bit enables the serial i/o port and initializes the port b ddr such that pb5 (sdo) is output, pb6 (sdi) is input and pb7 (sck) is input (slave mode only). the port b ddr can be altered subsequently as the application requires and the port b data register (except for pb5) can be manipulated as usual. however, these actions could affect the transmitted or received data. when spe is cleared, port b reverts to standard parallel i/o without affecting the port b data register or ddr. spe is readable and writable any time but clearing spe while a transmission is in progress will abort the transmission, reset the bit counter, and return port b to its normal i/o function. reset clears this bit. mstr master mode when set, this bit con?gures the siop for master mode. this means that the transmission is initiated by a write to the data register and the sck pin becomes an output providing a synchronous data clock at a ?xed rate of e (bus clock) divided by four. while the device is in master mode, the sdo and sdi pins do not change function. these pins behave exactly as they would in slave mode. reset clears this bit and con?gures the siop for slave operation. mstr may be set at any time regardless of the state of spe. clearing mstr will abort any transmission in progress. $0a 0 spe 0 mstr 0000 reset: 00000000 figure 7-3. siop control register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification simple serial input/output port mc68HC05P9A 7-4 rev. 2.0 7.2.2 siop status register (ssr) this register is located at address $000b and contains only two bits. spif serial peripheral interface flag this bit is set upon occurrence of the last rising clock edge and indicates that a data transfer has taken place. it has no effect on any further transmissions and can be ignored without problem. spif is cleared by reading the ssr with spif set followed by a read or write of the serial data register. if it is cleared before the last edge of the next byte, it will be set again. reset clears this bit. dcol data collision this is a read-only status bit which indicates that an invalid access to the data register has been made. this can occur any time after the ?rst falling edge of sck and before spif is set. a read or write of the data register during this time will result in invalid data being transmitted or received. dcol is cleared by reading the status register with spif set followed by a read or write of the data register. if the last part of the clearing sequence is done after another transmission has been started, dcol will be set again. if the dcol bit is set and the spif is not set, clearing the dcol requires turning the siop off then turning it back on. reset also clears this bit. $0b spif dcol 000000 reset: 00000000 figure 7-4. siop status register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification simple serial input/output port rev. 2.0 7-5 7.2.3 siop data register (sdr) this register is located at address $000c and is both the transmit and receive data register. this system is not double buffered and any write to this register will destroy the previous contents. the sdr can be read at any time, but if a transmission is in progress the results may be ambiguous. writes to the sdr while a transmission is in progress can cause invalid data to be transmitted and/or received. this register can be read and written only when the siop is enabled (spe=1). $0c reset: uuuuuuuu figure 7-5. siop data register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification simple serial input/output port mc68HC05P9A 7-6 rev. 2.0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification timer rev. 2.0 8-1 section 8 timer the timer consists of a 16-bit, software-programmable counter driven by a ?xed divide-by-four prescaler. this timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. pulse widths can vary from several microseconds to many seconds. refer to figure 8-1 for a timer block diagram. each speci?c functional segment (capability) is represented by two registers. these registers contain the high and low byte of that functional segment. generally, accessing the low byte of a speci?c timer function allows full control of that function; however, an access of the high byte inhibits that speci?c timer function until the low byte also is accessed. note the i bit in the ccr should be set while manipulating both the high and low byte register of a speci?c timer function to ensure that an interrupt does not occur. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification timer mc68HC05P9A 8-2 rev. 2.0 8.1 counter the key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. the prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 mhz. the counter is incremented during the low portion of the internal bus clock. software can read the counter at any time without affecting its value. the double-byte, free-running counter can be read from either of two locations, $18-$19 (counter register) or $1a-$1b (counter alternate register). a read from only the least signi?cant byte (lsb) of the free-running counter ($19, $1b) receives the count value at the time of the read. if a read of the free-running counter or counter alternate register ?rst addresses the most signi?cant byte (msb) ($18, $1a), the lsb ($19, $1b) is transferred to a buffer. this buffer value remains ?xed after the ?rst msb read, even if the user reads the msb several figure 8-1. timer block diagram input capture register clock internal bus output compare register high byte low byte $16 $17 /4 internal processor 16-bit free running counter counter alternate register 8-bit buffer high byte low byte $1a $1b $18 $19 high byte low byte $14 $15 output compare circuit overflow detect circuit edge detect circuit timer status reg. icf ocf tof $13 icie iedg olvl output level reg. reset timer control reg. $12 output level (tcmp) interrupt circuit toie ocie edge input (tcap) d clk c q f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification timer rev. 2.0 8-3 times. this buffer is accessed when reading the free-running counter or counter alternate register lsb ($19 or $1b) and, thus, completes a read sequence of the total counter value. in reading either the free-running counter or counter alternate register, if the msb is read, the lsb also must be read to complete the sequence. the counter alternate register differs from the counter register in one respect: aread of the counter register msb can clear the timer over?ow ?ag (tof). therefore, the counter alternate register can be read at any time without the possibility of missing timer over?ow interrupts due to clearing of the tof. the free-running counter is con?gured to $fffc during reset and is always a read-only register. during a power-on reset, the counter is also preset to $fffc and begins running after the oscillator start-up delay. because the free-running counter is 16 bits preceded by a ?xed divided-by-four prescaler, the value in the free-running counter repeats every 262,144 internal bus clock cycles. when the counter rolls over from $ffff to $0000, the tof bit is set. an interrupt can also be enabled when counter rollover occurs by setting its interrupt enable bit (toie). 8.2 output compare register the 16-bit output compare register is made up of two 8-bit registers at locations $16 (msb) and $17 (lsb). the output compare register is used for several purposes, such as indicating when a period of time has elapsed. all bits are readable and writable and are not altered by the timer hardware or reset. if the compare function is not needed, the two bytes of the output compare register can be used as storage locations. the output compare register contents are compared with the contents of the free- running counter continually, and if a match is found, the corresponding output compare ?ag (ocf) bit is set and the corresponding output level (olvl) bit is clocked to an output level register. the output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed timeout. an interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (ocie) is set. after a processor write cycle to the output compare register containing the msb ($16), the output compare function is inhibited until the lsb ($17) is also written. the user must write both bytes (locations) if the msb is written ?rst. a write made only to the lsb ($17) will not inhibit the compare function. the free-running counter is updated every four internal bus clock cycles. the minimum time required to update the output compare register is a function of the program rather than the internal hardware. the processor can write to either byte of the output compare register without affecting the other byte. the output level (olvl) bit is clocked to the output level register regardless of whether the output compare ?ag (ocf) is set or clear. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification timer mc68HC05P9A 8-4 rev. 2.0 8.3 input capture register two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a de?ned transition. the level transition which triggers the counter transfer is de?ned by the corresponding input edge bit (iedg). reset does not affect the contents of the input capture register. the result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. this delay is required for internal synchronization. resolution is one count of the free-running counter, which is four internal bus clock cycles. the free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture ?ag (icf) is set or clear. the input capture register always contains the free-running counter value that corresponds to the most recent input capture. after a read of the input capture register ($14) msb, the counter transfer is inhibited until the lsb ($15) is also read. this characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. a read of the input capture register lsb ($15) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification timer rev. 2.0 8-5 8.4 timer control register (tcr) $12 the tcr is a read/write register containing ?ve control bits. three bits control interrupts associated with the timer status register ?ags icf, ocf, and tof. icie input capture interrupt enable 1 = interrupt enabled 0 = interrupt disabled ocie output compare interrupt enable 1 = interrupt enabled 0 = interrupt disabled toie timer over?ow interrupt enable 1 = interrupt enabled 0 = interrupt disabled iedg input edge value of input edge determines which level transition on tcap pin will trigger free-running counter transfer to the input capture register 1 = positive edge 0 = negative edge reset does not affect the iedg bit (u=unaffected). olvl output level value of output level is clocked into output level register by the next successful output compare and will appear on the tcmp pin 1 = high output 0 = low output bits 2, 3, and 4 not used always read zero $12 icie ocie toie 0 0 0 iedg olvl reset: 00000000 figure 8-2. timer control register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification timer mc68HC05P9A 8-6 rev. 2.0 8.5 timer status register (tsr) $13 the tsr is a read-only register containing three status ?ag bits. icf input capture flag 1 = flag set when selected polarity edge is sensed by input capture edge detector 0 = flag cleared when tsr and input capture low register ($15) are accessed ocf output compare flag 1 = flag set when output compare register contents match the free- running counter contents 0 = flag cleared when tsr and output compare low register ($17) are accessed tof timer over?ow flag 1 = flag set when free-running counter transition from $ffff to $0000 occurs 0 = flag cleared when tsr and counter low register ($19) are accessed bits 0-4 not used always read zero accessing the timer status register satis?es the ?rst condition required to clear status bits. the remaining step is to access the register corresponding to the status bit. a problem can occur when using the timer over?ow function and reading the free- running counter at random times to measure an elapsed time. without incorporating the proper precautions into software, the timer over?ow ?ag could unintentionally be cleared if: 1. the timer status register is read or written when tof is set, and 2. the lsb of the free-running counter is read but not for the purpose of servicing the ?ag. the counter alternate register at address $1a and $1b contains the same value as the free-running counter (at address $18 and $19); therefore, this alternate register can be read at any time without affecting the timer over?ow ?ag in the timer status register. $13icfocftof00000 reset: u u u 00000 figure 8-3. timer status register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification timer rev. 2.0 8-7 8.6 timer during wait or halt mode the cpu clock halts during the wait or halt mode, but the timer remains active. if interrupts are enabled, a timer interrupt will cause the processor to exit the wait mode. 8.7 timer during stop mode in the stop mode, the timer stops counting and holds the last count value if stop is exited by an interrupt. if reset is used, the counter is forced to $fffc. during stop, if at least one valid input capture edge occurs at the tcap pin, the input capture detect circuit is armed. this does not set any timer ?ags wake up the mcu, but when the mcu does wake up, there is an active input capture ?ag and data from the ?rst valid edge that occurred during the stop mode. if reset is used to exit stop mode, then no input capture ?ag or data remains, even if a valid input capture edge occurred. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification timer mc68HC05P9A 8-8 rev. 2.0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification computer operating properly (cop) rev. 2.0 9-1 section 9 computer operating properly (cop) this device includes a watchdog cop feature as a mask option. the cop is implemented with an 18-bit ripple counter. this provides a timeout period of 64 milliseconds at a bus rate of 2 mhz. if the cop should timeout, a system reset will occur and the device will be re-initialized in the same fashion as a power-on reset (por) or external reset. 9.1 resetting the cop preventing a cop reset is done by writing a zero to the copr bit. this action will reset the counter and begin the timeout period again. the copr bit is bit 0 of address $1ff0. a read of address $1ff0 will access the user-de?ned rom data at that location. 9.2 cop during wait or halt mode the cop will continue to operate normally during wait or halt mode. the software should pull the device out of wait or halt mode periodically and reset the cop by writing a logic zero to the copr bit to prevent a cop reset. 9.3 cop during stop mode stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. the cop counter will be reset when stop mode is entered. if a reset is used to exit stop mode, the cop counter will be reset after the 4064 cycles of delay after stop mode. if an irq is used to exit stop mode, the cop counter will not be reset after the 4064-cycle delay and will have that many cycles already counted when control is returned to the program. note the halt mode is not intended for normal use. this feature is provided to keep the cop watchdog timer active in the event a stop instruction is inadvertently executed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification computer operating properly (cop) mc68HC05P9A 9-2 rev. 2.0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification analog-to-digital (a/d) converter rev. 2.0 10-1 section 10 analog-to-digital (a/d) converter this section describes the four-channel, 8-bit, multiplexed input, successive- approximation a/d converter. 10.1 conversion process the a/d conversion process is ratiometric, using two reference voltages, v rh and v ss . conversion accuracy is guaranteed only if v rh is equal to v dd . a multiplexer selects one of four analog input channels (an3, an2, an1, or an0) for sampling. a comparator successively compares the output of an internal digital-to-analog (d/a) converter to the sampled analog input. control logic changes the d/a converter input one bit at a time, starting with the most signi?cant bit (msb), until the d/a converter output matches the sampled analog input. the conversion is monotonic and has no missing codes. an analog input voltage equal to v rh converts to digital $ff; an input voltage greater than v rh converts to $ff with no over?ow. an analog input voltage equal to v ss converts to digital $00. for ratiometric conversions, the source of each analog input should use v rh as the supply voltage and be referenced to v ss . pins pc6Cpc3 are the four inputs to the multiplexer. each channel of conversion takes 32 internal clock cycles, and the clock frequency must be equal to or greater than 1 mhz. if the internal clock frequency is less than 1 mhz, the a/d internal rc oscillator (nominally 1.5 mhz) must be used for the a/d conversion clock. make this selection by setting the adrc bit in the a/d status and control register to logical one. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification analog-to-digital (a/d) converter mc68HC05P9A 10-2 rev. 2.0 10.2 a/d status and control register (adscr) the a/d status and control register contains a status ?ag and four writable control bits. ccf conversion complete flag this read-only bit is automatically set when an analog-to-digital conversion is complete, and a new result can be read from the a/d data register. ccf is automatically cleared when a new conversion begins or when either the a/d status and control register or the a/d data register is accessed. writing to or reading the a/d status and control register or the a/d data register starts a new conversion sequence. data from the previous conversion is overwritten regardless of the state of the ccf bit. while ccf is a logical zero, the requested a/d result is not yet available in the a/d data register. adrc a/d rc oscillator control when the rc oscillator is turned on, it requires a time (t adrc ) to stabilize, and results can be inaccurate during this time. if the internal clock rate is above 1 mhz, the ardc bit should be cleared. 1 = internal rc oscillator drives a/d converter 0 = internal clock drives a/d converter when the internal rc oscillator is being used as the a/d converter clock, two limitations apply: 1. because of the frequency tolerance of the rc oscillator and its asynchronism with the internal clock, the conversion complete ?ag (ccf) must be used to determine when a conversion sequence has been completed. 2. the conversion process runs at the nominal 1.5 mhz rate, but the conversion results must be transferred to the a/d data register synchronously with the internal clock; therefore, the conversion process is limited to a maximum of one channel every internal clock cycle. adon a/d on when the a/d is turned on, it requires a time (t adon ) for the current sources to stabilize. during this time, results can be inaccurate. 1 = a/d converter enabled 0 = a/d converter disabled bits 4C2 not used these bits are not used and read logical zero out of reset. logical zeros must be written to these bits when writing the a/d status and control register. $001e ccf adrc adon 0 0 0 ch1 ch0 reset: 00000000 figure 10-1. a/d status and control register (adscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification analog-to-digital (a/d) converter rev. 2.0 10-3 ch1Cch0 channel select these bits select one of the four a/d inputs (an3, an2, an1, or an0) for conversion. refer to table 10-1). to prevent excess power dissipation, do not use a port c pin as an analog input and a digital input at the same time. using one of the port c pins as the a/d converter input does not affect the ability to use the remaining port c pins as digital inputs. performing a digital read of a port c pin that is selected as an analog input returns a logical zero. 10.3 a/d data register (addr) the a/d data register is a read-only register that contains the result of the most recent a/d conversion. this register is updated each time the conversion complete ?ag (ccf) is set in the a/d status and control register. 10.4 a/d converter during wait mode the a/d converter continues to operate normally while the mcu is in wait mode. if the a/d converter is not being used, clear the adon and adrc bits in the a/d status and control register to decrease power consumption during wait mode. table 10-1. a/d input selection ch1:ch0 input selected 00 an0, port c bit 6 01 an1, port c bit 5 10 an2, port c bit 4 11 an3, port c bit 3 $001d bit 7 654321 bit 0 reset: a/d data register not affected by reset figure 10-2. a/d data register (addr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification analog-to-digital (a/d) converter mc68HC05P9A 10-4 rev. 2.0 10.5 a/d converter during stop or halt mode stop or halt mode disables the comparator and charge pump and aborts any conversion in progress or pending. when the mcu leaves stop mode, the built-in delay for oscillator startup allows enough time for the a/d circuits to stabilize. therefore, no software delays are needed after exiting from stop mode. when the mcu leaves halt mode, a software delay is needed since the mcu may exit from halt mode after only one internal clock cycle. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification self-check mode rev. 2.0 11-1 section 11 self-check mode the self-check program resides at mask rom locations $1f00 to $1fef. this program is designed to check the parts functionality with a minimum of support hardware. the cop subsystem is disabled in the self-check mode so that routines that feed the cop do not exist in the self-check program. the self-check mode is entered on the rising edge of reset if the irq pin is driven to double the supply voltage and the tcap/pd7 pin is at logic one. reset must be held low for 4064 cycles after por or for a time t rl for any other reset. after reset, the i/o, ram, rom, timer, and siop are tested. self-check results (using leds as monitors) are shown in table 11-1. it is not recommended that the user code use any of the self-check code. the self-check code is subject to change at any time to improve testability or manufacturability. table 11-1. self-check results pc2 pc1 pc0 remarks 0 0 1 bad i/o 0 1 0 bad ram 0 1 1 bad timer 1 0 0 bad rom 1 0 1 bad serial flashing good device all others bad device 0 indicates led is on; 1 indicates led is off. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification self-check mode mc68HC05P9A 11-2 rev. 2.0 figure 11-1. self-check circuit 10 k w v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27 28 21 22 23 24 25 26 v dd 4.7 k w reset irq pa5 pa4 pa3 pa2 pa1 pa0 pa6 pa7 sdo/pb5 sdi/pb6 sck/pb7 v ss 1 m f 20 pf 10 m w 4 mhz 20 pf pc0 v dd osc1 osc2 tcap/pd7 tcmp pd5 pc1 pc2 pc3 pc4 pc5 pc6 pc7 v dd v tst 20 19 18 17 16 15 10 k w 470 w 10 k w v tst = 10.0 v v dd = 5.0 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification instruction set rev. 2.0 12-1 section 12 instruction set this section describes the m68HC05P9A addressing modes and instruction types. 12.1 addressing modes the cpu uses eight addressing modes for ?exibility in accessing data. the addressing modes de?ne the manner in which the cpu ?nds the data required to execute an instruction. the eight addressing modes are the following: ? inherent ? immediate ? direct ? extended ? indexed, no offset ? indexed, 8-bit offset ? indexed, 16-bit offset ? relative 12.1.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry ?ag (sec) and increment accumulator (inca). inherent instructions require no memory address and are one byte long. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification instruction set mc68HC05P9A 12-2 rev. 2.0 12.1.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no memory address and are two bytes long. the opcode is the ?rst byte, and the immediate data value is the second byte. 12.1.3 direct direct instructions can access any of the ?rst 256 memory addresses with two bytes. the ?rst byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. brset and brclr are three-byte instructions that use direct addressing to access the operand and relative addressing to specify a branch destination. 12.1.4 extended extended instructions use only three bytes to access any address in memory. the ?rst byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. 12.1.5 indexed, no offset indexed instructions with no offset are one-byte instructions that can access data with variable addresses within the ?rst 256 memory locations. the index register contains the low byte of the conditional address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000C$00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or i/o location. 12.1.6 indexed, 8-bit offset indexed, 8-bit offset instructions are two-byte instructions that can access data with variable addresses within the ?rst 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the conditional address of the operand. these instructions can access locations $0000C$01fe. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification instruction set rev. 2.0 12-3 indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the ?rst 256 memory locations and could extend as far as location 510 ($01fe). the k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 12.1.7 indexed, 16-bit offset indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the conditional address of the operand. the ?rst byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. these instructions can address any location in memory. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing the motorola assembler determines the shortest form of indexed addressing. 12.1.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu ?nds the conditional branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, twos complement byte that gives a branching range of C128 to +127 bytes from the address of the next location after the branch instruction. when using the motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and veri?es that it is within the span of the branch. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification instruction set mc68HC05P9A 12-4 rev. 2.0 12.2 instruction types the mcu instructions fall into the following ?ve categories: ? register/memory instructions ? read-modify-write instructions ? jump/branch instructions ? bit manipulation instructions ? control instructions 12.2.1 register/memory instructions most of these instructions use two operands. one operand is in either the accumulator or the index register. the cpu ?nds the other operand in memory. table 12-1 lists the register/memory instructions. table 12-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification instruction set rev. 2.0 12-5 12.2.2 read-modify-write instructions these instructions read a memory location or a register, modify its contents, and write the modi?ed value back to the memory location or to the register. the test for negative or zero instruction (tst) is an exception to the read-modify-write sequence because it does not write a replacement value. table 12-2 lists the read-modify-write instructions. 12.2.3 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump to subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. all branch instructions use relative addressing. bit test and branch instructions cause a branch based on the state of any readable bit in the ?rst 256 memory locations. these three-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu ?nds the conditional branch destination by adding the table 12-2. read-modify-write instructions instruction mnemonic arithmetic shift left asl arithmetic shift right asr clear bit in memory bclr set bit in memory bset clear clr complement (ones complement) com decrement dec increment inc logical shift left lsl logical shift right lsr negate (twos complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification instruction set mc68HC05P9A 12-6 rev. 2.0 third byte to the program counter if the speci?ed bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from C128 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register. table 12-3 lists the jump and branch instructions. table 12-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification instruction set rev. 2.0 12-7 12.2.4 bit manipulation instructions the cpu can set or clear any writable bit in the ?rst 256 bytes of memory. port registers, port data direction registers, timer registers, and on-chip ram locations are in the ?rst 256 bytes of memory. the cpu can also test and branch based on the state of any bit in any of the ?rst 256 memory locations. bit manipulation instructions use direct addressing. table 12-4 lists these instructions. 12.2.5 control instructions these register reference instructions control cpu operation during program execution. control instructions, listed in table 12-5, use inherent addressing. table 12-4. bit manipulation instructions instruction mnemonic clear bit bclr branch if bit clear brclr branch if bit set brset set bit bset table 12-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification instruction set mc68HC05P9A 12-8 rev. 2.0 12.3 instruction set summary table 12-6 is an alphabetical list of all m68hc05 instructions and shows the effect of each instruction on the condition code register. table 12-6. instruction set summary source form operation description effect on ccr address mode opcode operand cycles hinzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a ? (a) + (m) + (c) imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a ? (a) + (m) imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a ? (a) (m) imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bclr n opr clear bit n mn ? 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 beq rel branch if equal pc ? (pc) + 2 + rel ? z = 1 rel 27 rr 3 c b0 b7 0 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification instruction set rev. 2.0 12-9 bhcc rel branch if half-carry bit clear pc ? (pc) + 2 + rel ? h = 0 rel 28 rr 3 bhcs rel branch if half-carry bit set pc ? (pc) + 2 + rel ? h = 1 rel 29 rr 3 bhi rel branch if higher pc ? (pc) + 2 + rel ? c z = 0 rel 22 rr 3 bhs rel branch if higher or same pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bih rel branch if irq pin high pc ? (pc) + 2 + rel ? irq = 1 rel 2f rr 3 bil rel branch if irq pin low pc ? (pc) + 2 + rel ? irq = 0 rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff p 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 bls rel branch if lower or same pc ? (pc) + 2 + rel ? c z = 1 rel 23 rr 3 bmc rel branch if interrupt mask clear pc ? (pc) + 2 + rel ? i = 0 rel 2c rr 3 bmi rel branch if minus pc ? (pc) + 2 + rel ? n = 1 rel 2b rr 3 bms rel branch if interrupt mask set pc ? (pc) + 2 + rel ? i = 1 rel 2d rr 3 bne rel branch if not equal pc ? (pc) + 2 + rel ? z = 0 rel 26 rr 3 bpl rel branch if plus pc ? (pc) + 2 + rel ? n = 0 rel 2a rr 3 bra rel branch always pc ? (pc) + 2 + rel ? 1 = 1 rel 20 rr 3 brclr n opr rel branch if bit n clear pc ? (pc) + 2 + rel ? mn = 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brset n opr rel branch if bit n set pc ? (pc) + 2 + rel ? mn = 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ? (pc) + 2 + rel ? 1 = 0 rel 21 rr 3 table 12-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification instruction set mc68HC05P9A 12-10 rev. 2.0 bset n opr set bit n mn ? 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc ? (pc) + 2; push (pcl) sp ? (sp) C 1; push (pch) sp ? (sp) C 1 pc ? (pc) + rel rel ad rr 6 clc clear carry bit c ? 0 0 inh 98 2 cli clear interrupt mask i ? 0 0 inh 9a 2 clr opr clra clrx clr opr ,x clr ,x clear byte m ? $00 a ? $00 x ? $00 m ? $00 m ? $00 0 1 dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) C (m) imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (ones complement) m ? ( ) = $ff C (m) a ? ( ) = $ff C (m) x ? ( ) = $ff C (m) m ? ( ) = $ff C (m) m ? ( ) = $ff C (m) 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) C (m) 1 imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m ? (m) C 1 a ? (a) C 1 x ? (x) C 1 m ? (m) C 1 m ? (m) C 1 dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a ? (a) ? (m) imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 table 12-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc m a x m m f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification instruction set rev. 2.0 12-11 inc opr inca incx inc opr ,x inc ,x increment byte m ? (m) + 1 a ? (a) + 1 x ? (x) + 1 m ? (m) + 1 m ? (m) + 1 dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc ? jump address dir ext ix2 ix1 ix bc c c d c ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? (pc) + n (n = 1, 2, or 3) push (pcl); sp ? (sp) C 1 push (pch); sp ? (sp) C 1 pc ? conditional address dir ext ix2 ix1 ix bd c d d d ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a ? (m) imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x ? (m) imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a ? (x) (a) 0 0 inh 42 11 neg opr nega negx neg opr ,x neg ,x negate byte (twos complement) m ? C(m) = $00 C (m) a ? C(a) = $00 C (a) x ? C(x) = $00 C (x) m ? C(m) = $00 C (m) m ? C(m) = $00 C (m) dir inh inh ix1 ix 30 40 50 60 70 ii ff 5 3 3 6 5 nop no operation inh 9d 2 table 12-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 0 b0 b7 c 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification instruction set mc68HC05P9A 12-12 rev. 2.0 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a ? (a) (m) imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp ? $00ff inh 9c 2 rti return from interrupt sp ? (sp) + 1; pull (ccr) sp ? (sp) + 1; pull (a) sp ? (sp) + 1; pull (x) sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 80 6 rts return from subroutine sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a ? (a) C (m) C (c) imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c ? 1 1 inh 99 2 sei set interrupt mask i ? 1 1 inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m ? (a) dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin 0 inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m ? (x) dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 table 12-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification instruction set rev. 2.0 12-13 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a ? (a) C (m) imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc ? (pc) + 1; push (pcl) sp ? (sp) C 1; push (pch) sp ? (sp) C 1; push (x) sp ? (sp) C 1; push (a) sp ? (sp) C 1; push (ccr) sp ? (sp) C 1; i ? 1 pch ? interrupt vector high byte pcl ? interrupt vector low byte 1 inh 83 10 tax transfer accumulator to index register x ? (a) inh 97 2 tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) C $00 dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a ? (x) inh 9f 2 wait stop cpu clock and enable interrupts inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow flag pc program counter ccr condition code register pch program counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing rr relative program counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry flag z zero flag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode ? logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode C( ) negation (twos complement) ix1 indexed, 8-bit offset addressing mode ? loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative flag set or cleared n any bit not affected table 12-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
instruction set mc68HC05P9A 12-14 rev. 2.0 table 12-7. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789 abcdef 0 5 brset0 3 dir 5 bset0 2 dir 3 bra 2 rel 5 neg 2 dir 3 nega 1 inh 3 negx 1 inh 6 neg 2 ix1 5 neg 1ix 9 rti 1 inh 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 5 sub 3 ix2 4 sub 2 ix1 3 sub 1ix 0 1 5 brclr0 3 dir 5 bclr0 2 dir 3 brn 2 rel 6 rts 1 inh 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 5 cmp 3 ix2 4 cmp 2 ix1 3 cmp 1ix 1 2 5 brset1 3 dir 5 bset1 2 dir 3 bhi 2 rel 11 mul 1 inh 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 5 sbc 3 ix2 4 sbc 2 ix1 3 sbc 1ix 2 3 5 brclr1 3 dir 5 bclr1 2 dir 3 bls 2 rel 5 com 2 dir 3 coma 1 inh 3 comx 1 inh 6 com 2 ix1 5 com 1ix 10 swi 1 inh 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 5 cpx 3 ix2 4 cpx 2 ix1 3 cpx 1ix 3 4 5 brset2 3 dir 5 bset2 2 dir 3 bcc 2 rel 5 lsr 2 dir 3 lsra 1 inh 3 lsrx 1 inh 6 lsr 2 ix1 5 lsr 1ix 2 and 2 imm 3 and 2 dir 4 and 3 ext 5 and 3 ix2 4 and 2 ix1 3 and 1ix 4 5 5 brclr2 3 dir 5 bclr2 2 dir 3 bcs/blo 2 rel 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 5 bit 3 ix2 4 bit 2 ix1 3 bit 1ix 5 6 5 brset3 3 dir 5 bset3 2 dir 3 bne 2 rel 5 ror 2 dir 3 rora 1 inh 3 rorx 1 inh 6 ror 2 ix1 5 ror 1ix 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 5 lda 3 ix2 4 lda 2 ix1 3 lda 1ix 6 7 5 brclr3 3 dir 5 bclr3 2 dir 3 beq 2 rel 5 asr 2 dir 3 asra 1 inh 3 asrx 1 inh 6 asr 2 ix1 5 asr 1ix 2 tax 1 inh 4 sta 2 dir 5 sta 3 ext 6 sta 3 ix2 5 sta 2 ix1 4 sta 1ix 7 8 5 brset4 3 dir 5 bset4 2 dir 3 bhcc 2 rel 5 asl/lsl 2 dir 3 asla/lsla 1 inh 3 aslx/lslx 1 inh 6 asl/lsl 2 ix1 5 asl/lsl 1ix 2 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 5 eor 3 ix2 4 eor 2 ix1 3 eor 1ix 8 9 5 brclr4 3 dir 5 bclr4 2 dir 3 bhcs 2 rel 5 rol 2 dir 3 rola 1 inh 3 rolx 1 inh 6 rol 2 ix1 5 rol 1ix 2 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 5 adc 3 ix2 4 adc 2 ix1 3 adc 1ix 9 a 5 brset5 3 dir 5 bset5 2 dir 3 bpl 2 rel 5 dec 2 dir 3 deca 1 inh 3 decx 1 inh 6 dec 2 ix1 5 dec 1ix 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 5 ora 3 ix2 4 ora 2 ix1 3 ora 1ix a b 5 brclr5 3 dir 5 bclr5 2 dir 3 bmi 2 rel 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 5 add 3 ix2 4 add 2 ix1 3 add 1ix b c 5 brset6 3 dir 5 bset6 2 dir 3 bmc 2 rel 5 inc 2 dir 3 inca 1 inh 3 incx 1 inh 6 inc 2 ix1 5 inc 1ix 2 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix c d 5 brclr6 3 dir 5 bclr6 2 dir 3 bms 2 rel 4 tst 2 dir 3 tsta 1 inh 3 tstx 1 inh 5 tst 2 ix1 4 tst 1ix 2 nop 1 inh 6 bsr 2 rel 5 jsr 2 dir 6 jsr 3 ext 7 jsr 3 ix2 6 jsr 2 ix1 5 jsr 1ix d e 5 brset7 3 dir 5 bset7 2 dir 3 bil 2 rel 2 stop 1 inh 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 5 ldx 3 ix2 4 ldx 2 ix1 3 ldx 1ix e f 5 brclr7 3 dir 5 bclr7 2 dir 3 bih 2 rel 5 clr 2 dir 3 clra 1 inh 3 clrx 1 inh 6 clr 2 ix1 5 clr 1ix 2 wait 1 inh 2 txa 1 inh 4 stx 2 dir 5 stx 3 ext 6 stx 3 ix2 5 stx 2 ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3 dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb m s b lsb msb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification electrical specifications rev. 2.0 13-1 section 13 electrical specifications 13.1 maximum ratings (voltages referenced to v ss this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?elds; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., either v ss or v dd ). 13.2 thermal characteristics rating symbol value unit supply voltage v dd -0.3 to +7.0 v input voltage v in v ss -0.3 to v dd +0.3 v self-check modes ( irq pin only) v in v ss -0.3 to 2 x v dd +0.3 v current drain per pin excluding v dd and v ss i25ma operating temperature range 68HC05P9Ap (standard) 68HC05P9Acp (extended) 68HC05P9Avp (automotive) 68HC05P9Amp (automotive) t a t l to t h 0 to +70 -40 to +85 -40 to +105 -40 to +125 c storage temperature range t stg -65 to +150 c characteristic symbol value unit thermal resistance plastic dip plastic soic q ja 60 71 c/w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification electrical specifications mc68HC05P9A 13-2 rev. 2.0 13.3 dc electrical characteristics table 13-1. dc electrical characteristics (v dd = 5 v) (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = -40 c to +125 c, unless otherwise noted) characteristic symbol min typ max unit output voltage i load = 10.0 m a i load = -10.0 m a v ol v oh v dd -0.1 0.1 v output high voltage (i load = -0.8 ma) pa0-pa7, pb5-pb7, pc2-pc7, pd5, tcmp (i load = -5.0 ma) pc0-pc1 v oh v oh v dd -0.8 v dd -0.8 v output low voltage (i load = 1.6 ma) pa0-pa7, pb5-pb7, pc2-pc7, pd5, tcmp (i load = 15 ma) pc0-pc1 v ol v ol 0.4 0.4 v input high voltage pa0-pa7, pb5-pb7, pc0-pc7, pd5, tcap/pd7, irq, reset, osc1 v ih 0.7 v dd v dd v input low voltage pa0-pa7, pb5-pb7, pc0-pc7, pd5, tcap/pd7, irq, reset, osc1 v il v ss 0.2 v dd v supply current run (a/d enabled) wait (a/d enabled) wait (a/d disabled)/halt stop 25 c 0 c to +70 c -40 c to +85 c -40 c to +105 c -40 c to +125 c i dd 3.3 1.7 1.0 2 tbd tbd tbd 5 tbd tbd tbd 100 ma ma ma m a m a m a m a m a i/o ports hi-z leakage current pa0-pa7, pb5-pb7, pc0-pc2, pd5 i il 10 m a a/d ports hi-z leakage current pc3Cpc7 i oz 1 m a input current reset, irq, osc1, tcap/pd7 i in 1 m a i/o ports switch resistance (pullup enabled pa0-pa7) r pta tbd 15 tbd k w capacitance ports (as input or output) reset, irq c out c in 12 8 pf notes: 1. all values shown reflect average measurements. 2. typical values at midpoint of voltage range, 25 c. 3. wait i dd : only timer system active. 4. run (operating) i dd , wait i dd : measured using external square wave clock source (f osc = 4.2 mhz), all inputs 0.2 v from rail; no dc loads, less than 50 pf on all outputs, c l = 20 pf on osc2. 5. wait, stop i dd : all ports configured as inputs, v il = 0.2 v, v ih = v dd -0.2 v. 6. wait i dd is affected linearly by the osc2 capacitance. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification electrical specifications rev. 2.0 13-3 table 13-2. dc electrical characteristics (v dd = 3.3 v) (v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = -40 c to +125 c, unless otherwise noted) characteristic symbol min typ max unit output voltage i load = 10.0 m a i load = -10.0 m a v ol v oh v dd -0.1 0.1 v output high voltage (i load = -0.2 ma) pa0-pa7, pb5-pb7, pc2-pc7, pd5, tcmp (i load = -1.5 ma) pc0-pc1 v oh v oh v dd -0.3 v dd -0.3 v output low voltage (i load = 0.4 ma) pa0-pa7, pb5-pb7, pc2-pc7, pd5, tcmp (i load = 6.0 ma) pc0-pc1 v ol v ol 0.3 0.3 v input high voltage pa0-pa7, pb5-pb7, pc0-pc7, pd5, tcap/pd7, irq, reset, osc1 v ih 0.7 v dd v dd v input low voltage pa0-pa7, pb5-pb7, pc0-pc7, pd5, tcap/pd7, irq, reset, osc1 v il v ss 0.2 v dd v supply current run (a/d enabled) wait (a/d enabled) wait (a/d disabled)/halt stop 25 c 0 c to +70 c -40 c to +85 c -40 c to +105 c -40 c to +125 c i dd 1.2 0.8 0.4 1 tbd tbd tbd 3 tbd tbd tbd 70 ma ma ma m a m a m a m a m a i/o ports hi-z leakage current pa0-pa7, pb5-pb7, pc0-pc2, pd5 i il 10 m a a/d ports hi-z leakage current pc3Cpc7 i oz 1 m a input current reset, irq, osc1, tcap/pd7 i in 1 m a i/o ports switch resistance (pullup enabled pa0-pa7) r pta tbd 25 tbd k w capacitance ports (as input or output) reset, irq c out c in 12 8 pf notes: 1. all values shown reflect average measurements. 2. typical values at midpoint of voltage range, 25 c. 3. wait i dd : only timer system active. 4. run (operating) i dd , wait i dd : measured using external square wave clock source (f osc = 2.0 mhz), all inputs 0.2 v from rail; no dc loads, less than 50 pf on all outputs, c l = 20 pf on osc2. 5. wait, stop i dd : all ports configured as inputs, v il = 0.2 v, v ih = v dd -0.2 v. 6. wait i dd is affected linearly by the osc2 capacitance. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification electrical specifications mc68HC05P9A 13-4 rev. 2.0 13.4 a/d converter characteristics table 13-3. a/d converter characteristics characteristic min max unit resolution 8 8 bit absolute accuracy (4.0 v > v rh > v dd ) (see note 1) 1C1/2 lsb conversion range v rh v ss v ss v rh v dd v conversion time (includes sampling time) external clock (xtal) internal rc oscillator (adrc = 1) 32 32 32 t ad m s power-up time 100 m s monotonicity inherent (within total error) zero input reading (v in = 0 v) 00 01 hex full-scale reading (v in = v rh ) ff ff hex sample acquisition time (see note 2) external clock (xtal) internal rc oscillator (adrc = 1) 12 12 12 t ad m s input capacitance pc3/an3Cpc6/an0 12pf analog input voltage v ss v rh v input leakage (see note 4) an0Can3 v rh 1 1 m a notes: 1. a/d accuracy may decrease proportionately as v rh is reduced below 4.0 v. 2. source impedances greater than 10 k w adversely affect internal rc charging time during input sampling. 3. t ad = t cyc if clock source is mcu. 4. the external system error caused by input leakage current is approximately equal to the product of r source and input current. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification electrical specifications rev. 2.0 13-5 13.5 siop timing table 13-4. siop timing (v dd = 5 v) (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = -40 c to +125 c, unless otherwise noted) table 13-5. siop timing (v dd = 3.3 v) (v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = -40 c to +125 c, unless otherwise noted) num. characteristic symbol min max unit operating frequency master slave f op(m) f op(s) 0.25 dc 0.25 0.25 f op 1 cycle time master slave t cyc(m) t cyc(s) 4.0 4.0 4.0 t cyc 2 clock (sck) low time t cyc 932 ns 3 sdo data valid time t v 200 ns 4 sdo hold time t ho 0ns 5 sdi setup time t s 100 ns 6 sdi hold time t h 100 ns note: f op = 2.1 mhz maximum num. characteristic symbol min max unit operating frequency master slave f op(m) f op(s) 0.25 dc 0.25 0.25 f op 1 cycle time master slave t cyc(m) t cyc(s) 4.0 4.0 4.0 t cyc 2 clock (sck) low time t cyc 1980 ns 3 sdo data valid time t v 400 ns 4 sdo hold time t ho 0ns 5 sdi setup time t s 200 ns 6 sdi hold time t h 200 ns note: f op = 1.0 mhz maximum sdo bit 0 bit 1 bit 6 sck bit 7 sdi bit 0 bit 1 bit 6 bit 7 1 2 3 4 5 6 figure 13-1. siop timing diagram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification electrical specifications mc68HC05P9A 13-6 rev. 2.0 13.6 control timing table 13-6. control timing (v dd = 5 v) (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = -40 c to +125 c, unless otherwise noted table 13-7. control timing (v dd = 3.3 v) (v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = -40 c to +125 c, unless otherwise noted characteristic symbol min max unit frequency of operation crystal option external clock option f osc dc 4.2 4.2 mhz internal operating frequency crystal (f osc ? 2) external clock (f osc ? 2) f op dc 2.1 2.1 mhz cycle time t cyc 480 ns crystal oscillator startup time t oxov 100 ms stop recovery startup time (crystal oscillator) t ilch 100 ms reset pulse width t rl 1.5 t cyc interrupt pulse width low (edge-triggered) t ilih 125 ns interrupt pulse period t ilil *t cyc osc1 pulse width t oh, t ol 90 ns rc oscillator stabilization time t rcon 5 m s a/d on current stabilization time t adon 100 m s *the minimum period t ilil should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc . characteristic symbol min max unit frequency of operation crystal option external clock option f osc dc 2.0 2.0 mhz internal operating frequency crystal (f osc ? 2) external clock (f osc ? 2) f op dc 1.0 1.0 mhz cycle time t cyc 1000 ns crystal oscillator startup time t oxov 100 ms stop recovery startup time (crystal oscillator) t ilch 100 ms reset pulse width, excluding powerup t rl 1.5 t cyc interrupt pulse width low (edge-triggered) t ilih 250 ns interrupt pulse period t ilil *t cyc osc1 pulse width t oh, t ol 200 ns *the minimum period t ilil should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification electrical specifications rev. 2.0 13-7 figure 13-2. stop recovery timing figure 13-3. external interrupt timing 1fff 1ffe 1ffe 1ffe 1ffe 1ffe 4 reset or interrupt vector fetch internal clock irq 3 osc 1 irq 2 internal address bus reset notes: 1. represents the internal clocking of the osc1 pin. 2. irq pin edgeCsensitive mask option. 3. irq pin levelC and edgeCsensitive mask option. 4. reset vector address shown for timing example. t rl t ilih 4064 t cyc ? ? ? ilih t ilil t ilih t normally used with wireCored connection edge - sensit ive trigger condition th e m in im um pu ls e wid th ( t )is either 125 ns (v = 5 v) or 250 ns (v = 3 v). the pe ri od t should not be less than the number of t cy cles i t takes to execute the interr upt service routine plus 19 t c ycl es . dd dd ilih ilil cyc cyc level - sensitive trigger condition if after servicing an interrupt the irq re ma in s l ow , t h en t he ne xt i nt e rru pt is re co gn i zed . irq (pin) irq n irq 1 rq (mcu) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification electrical specifications mc68HC05P9A 13-8 rev. 2.0 figure 13-4. power-on reset timing figure 13-5. external reset timing sc1pin v dd 4064 t cyc in t e rn al clock in t e rn al address bus in t e rn al data bus 1fff 1ffe 1ffe 1ffe 1ffe new pcl new pch 1ffe 1ffe 1. in terna l clock, in tern al ad dre ss bu s, a nd in te rn al d ata bu s sign als a re no t a vailab le e xterna lly. 2. an internal por reset is triggered as v rises through a threshold (typically 1-2 v). v dd threshold (typically 1-2 v) t vddr dd notes: nternal clock nternal ddress bus reset notes: 1. in terna l clock, in tern al ad dre ss bu s, a nd in te rn al d ata bu s sign als a re no t a vailab le e xterna lly. 2. the ne xt risin g edg e of t he inte rn al p ro cesso r clo ck a fter t he rising ed ge of rese t in itiate s th e rese t se qu en ce. t rl new pc dummy nternal data bus new pc op code 1fff new pcl 1ffe new pch 1ffe 1ffe 1ffe f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification mechanical specifications rev. 2.0 14-1 section 14 mechanical specifications this section describes the dimensions of the dual in-line package (dip) and small outline integrated circuit (soic) mcu packages. 14.1 28-pin plastic dual in-line package (case 710-02)

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general release specification mechanical specifications mc68hc0p9a 14-2 rev. 2.0 14.2 28-pin small outline integrated circuit package (case 751f-04)

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$" !" ! " !" # !" !! $ ! $" ! ! -a- -b- 114 15 28 -t- c m j -t- k 26x g 28x d 14x p r x 45 ? ! f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification ordering information rev. 2.0 15-1 section 15 ordering information this section contains instructions for ordering custom-masked rom mcus. 15.1 mcu ordering forms to initiate an order for a rom-based mcu, ?rst obtain the current ordering form for the mcu from a motorola representative. submit the following items when ordering mcus: ? a current mcu ordering form that is completely ?lled out (contact your motorola sales of?ce for assistance.) ? a copy of the customer speci?cation if the customer speci?cation deviates from the motorola speci?cation for the mcu ? customers application program on one of the media listed in 15.2 application program media the current mcu ordering form is also available through the motorola freeware bulletin board service (bbs). the telephone number is (512) 891-free. after making the connection, type bbs in lower-case letters. then press the return key to start the bbs software. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification ordering information mc68HC05P9A 15-2 rev. 2.0 15.2 application program media please deliver the application program to motorola in one of the following media: ? macintosh 1 3 1/2-inch diskette (double-sided 800k or double-sided high-density 1.4m) ? ms-dos 2 or pc-dos tm 3 3 1/2-inch diskette (double-sided 720k or double-sided high-density 1.44m) ? ms-dos or pc-dos tm 5 1/4-inch diskette (double-sided double- density 360k or double-sided high-density 1.2m) use positive logic for data and addresses. when submitting the application program on a diskette, clearly label the diskette with the following information: ? customer name ? customer part number ? project or product name ? file name of object code ? date ? name of operating system that formatted diskette ? formatted capacity of diskette on diskettes, the application program must be in motorolas s-record format (s1 and s9 records), a character-based object ?le format generated by m6805 cross assemblers and linkers. note begin the application program at the ?rst user rom location. program addresses must correspond exactly to the available on-chip user rom addresses as shown in the memory map. write $00 in all non-user rom locations or leave all non-user rom locations blank . refer to the current mcu ordering form for additional requirements. motorola may request pattern re- submission if non-user areas contain any non-zero code. 1. macintosh is a registered trademark of apple computer, inc. 2. ms-dos is a registered trademark of microsoft corporation. 3. pc-dos is a trademark of international business machines corporation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification ordering information rev. 2.0 15-3 if the memory map has two user rom areas with the same address, then write the two areas in separate ?les on the diskette. label the diskette with both ?le names. in addition to the object code, a ?le containing the source code can be included. motorola keeps this code con?dential and uses it only to expedite rom pattern generation in case of any dif?culty with the object code. label the diskette with the ?le name of the source code. 15.3 rom program veri?cation the primary use for the on-chip rom is to hold the customers application program. the customer develops and debugs the application program and then submits the mcu order along with the application program. motorola inputs the customers application program code into a computer program that generates a listing verify ?le. the listing verify ?le represents the memory map of the mcu. the listing verify ?le contains the user rom code and may also contain non-user rom code, such as self-check code. motorola sends the customer a computer printout of the listing verify ?le along with a listing verify form. to aid the customer in checking the listing verify ?le, motorola will program the listing verify ?le into customer-supplied blank preformatted macintosh or dos disks. all original pattern media are ?led for contractual purposes and are not returned. check the listing verify ?le thoroughly, then complete and sign the listing verify form and return the listing verify form to motorola. the signed listing verify form constitutes the contractual agreement for the creation of the custom mask. 15.4 rom veri?cation units (rvus) after receiving the signed listing verify form, motorola manufactures a custom photographic mask. the mask contains the customers application program and is used to process silicon wafers. the application program cannot be changed after the manufacture of the mask begins. motorola then produces 10 mcus, called rvus, and sends the rvus to the customer. rvus are usually packaged in unmarked ceramic and tested to 5 vdc at room temperature. rvus are not tested to environmental extremes because their sole purpose is to demonstrate that the customers user rom pattern was properly implemented. the 10 rvus are free of charge with the minimum order quantity. these units are not to be used for quali?cation or production. rvus are not guaranteed by motorola quality assurance. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
general release specification ordering information mc68HC05P9A 15-4 rev. 2.0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006
hc05p9agrs/d motorola, inc., 1995 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . archived by freescale semiconductor, inc. 2006

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